Production of semiconductor integrated circuits and other microelectronic devices from workpieces such as semiconductor wafers typically requires formation of one or more metal layers on the wafer. These metal layers are used, for example, to electrically interconnect the various devices of the integrated circuit. Further, the structures formed from the metal layers may constitute microelectronic devices such as read/write heads, etc.
The microelectronic manufacturing industry has applied a wide range of metals to form such structures. These metals include, for example, nickel, tungsten, solder, platinum, and copper. Further, a wide range of processing techniques have been used to deposit such metals. These techniques include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, and electroless plating. Of these techniques, electroplating and electroless plating tend to be the most economical and, as such, the most desirable. Electroplating and electroless plating can be used in the deposition of blanket metal layers as well as patterned metal layers.
One of the most popular process sequences used by the microelectronic manufacturing industry to deposit a metal onto semiconductor wafers is referred to as “damascene” processing. In such processing holes, commonly called “vias”, trenches and/or other recesses are formed onto a workpiece and filled with a metal, such as copper. In the damascene process, the wafer is first provided with a metallic seed layer which is used to conduct electrical current during a subsequent metal electroplating step. If a metal such as copper is used, the seed layer is disposed over a barrier layer material, such as Ti, TiN, etc. The seed layer is a very thin layer of metal which can be applied using one or more of several processes. For example, the seed layer of metal can be laid down using physical vapor deposition or chemical vapor deposition processes to produce a layer on the order of 1,000 angstroms thick. The seed layer can advantageously be formed of copper, gold, nickel, palladium, or other metals. The seed layer is formed over a surface which is convoluted by the presence of the vias, trenches, or other recessed device features.
A metal layer is then electroplated onto the seed layer in the form of a blanket layer. The blanket layer is plated to form an overlying layer, with the goal of providing a metal layer that fills the trenches and vias and extends a certain amount above these features. Such a blanket layer will typically have a thickness on the order of 10,000 to 15,000 angstroms (1-1.5 microns).
After the blanket layer has been electroplated onto the semiconductor wafer, excess metal material present outside of the vias, trenches, or other recesses is removed. The metal is removed to provide a resulting pattern of metal layer in the semiconductor integrated circuit being formed. The excess plated material can be removed, for example, using chemical mechanical planarization. Chemical mechanical planarization is a processing step which uses the combined action of a chemical removal agent and an abrasive which grinds and polishes the exposed metal surface to remove undesired parts of the metal layer applied in the electroplating step.
The electroplating of the semiconductor wafers takes place in a reactor assembly. In such an assembly an anode electrode is disposed in a plating bath, and the wafer with the seed layer thereon is used as a cathode. Only a lower face of the wafer contacts the surface of the plating bath. The wafer is held by a support system that also conducts the requisite electroplating power (e.g., cathode current) to the wafer. The support system may comprise conductive fingers that secure the wafer in place and also contact the wafer seed layer in order to conduct electrical current for the plating operation. One embodiment of a reactor assembly is disclosed in U.S. Ser. No. 08/988,333 filed Sep. 30, 1997 now U.S. Pat. No. 5,985,126, entitled “Semiconductor Plating System Workpiece Support Having Workpiece—Engaging Electrodes With Distal Contact Part and Dielectric Cover.”
Several technical problems must be overcome in designing reactors used in the electroplating of semiconductor wafers. Utilization of a small number of discrete electrical contacts (e.g., 6 contacts) with the seed layer about the perimeter of the wafer ordinarily produces higher current densities near the contact points than at other portions of the wafer. This non-uniform distribution of current across the wafer, in turn, causes non-uniform deposition of the plated metallic material. Current thieving, effected by the provision of electrically-conductive elements other than those which contact the seed layer, can be employed near the wafer contacts to minimize such non-uniformity. But such thieving techniques add to the complexity of electroplating equipment, and increase maintenance requirements.
Another problem with electroplating of wafers concerns efforts to prevent the electric contacts themselves from being plated during the electroplating process. Any material plated to the electrical contacts must be removed to prevent changing contact performance. While it is possible to provide sealing mechanisms for discrete electrical contacts, such arrangements typically cover a significant area of the wafer surface, and can add complexity to the electrical contact design.
In addressing a further problem, it is sometimes desirable to prevent electroplating on the exposed barrier layer near the edge of the semiconductor wafer. Electroplated material may not adhere well to the exposed barrier layer material, and is therefore prone to peeling off in subsequent wafer processing steps. Further, metal that is electroplated onto the barrier layer within the reactor may flake off during the electroplating process thereby adding particulate contaminants to the electroplating bath. Such contaminants can adversely affect the overall electroplating process.
The specific metal to be electroplated can also complicate the electroplating process. For example, electroplating of certain metals typically requires use of a seed layer having a relatively high electrical resistance. As a consequence, use of the typical plurality of electrical wafer contacts (for example, six (6) discrete contacts) may not provide adequate uniformity of the plated metal layer on the wafer.
Beyond the contact related problems discussed above, there are also other problems associated with electroplating reactors. As device sizes decrease, the need for tighter control over the processing environment increases. This includes control over the contaminants that affect the electroplating process. The moving components of the reactor, which tend to generate such contaminants, should therefore be subject to strict isolation requirements.
Still further, existing electroplating reactors are often difficult to maintain and/or reconfigure for different electroplating processes. Such difficulties must be overcome if an electroplating reactor design is to be accepted for large-scale manufacturing.
One aspect of the present invention is directed to an improved electroplating apparatus having one or more of the following features: an improved workpiece contact assembly, a processing head having a quick-disconnect contact assembly construction, and/or a processing head having effective isolation of the moving components from the processing environment.
One drawback associated with copper deposition by electroplating is the fact that for very small features on microelectronic workpieces (sub 0.1 micron features), copper deposition by electroplating can lack conformality with the side walls of high aspect ratio vias and trenches, and can produce voids in the formed interconnects and plugs (vias). This is often due to the non-conformality of the copper seed layer deposited by PVD or CVD as a result, the seed layer may not be thick enough to carry the current to the bottom of high aspect ratio features.
An alternate process for depositing copper onto a microelectronic workpiece is known as “electroless” plating. A method of electroless plating of copper metallization onto microelectronic workpieces is disclosed in the article “Sub-Half Micron Electroless Cu Metallization,” by V. M. Dubin, et al., as published in the Materials Research Society Symposium Proceedings, volume 427, Advances Metallization For Future ULSI, 1996, herein incorporated by reference. The article describes the potential advantages of electroless Cu metallization as including lower tool costs, lower processing temperatures, higher quality deposits, superior uniformity of plating, and better via/trench filling capability.
According to the disclosed procedure, a blanket electroless Cu deposition was performed for via and trench filling on a workpiece having a Cu seed layer. The Cu seed layer was previously deposited by sputtering or contact displacement (wet activation process). An aluminum sacrificial layer was sputtered onto the Cu seed layer. Collimated Ti/N, uncollimated Ti, and uncollimated. Ta were used as diffusion barrier/adhesion promoter layers. After the electroless deposition of the Cu layer, chemical/mechanical polishing of the copper layer was performed to obtain inlaid copper metallization. A selective electroless CoW passivation layer was deposited on the inlaid Cu metallization.
According to the method disclosed in the foregoing article, the etching of the Al sacrificial layer in the same electroless Cu plating bath without transferring the wafer results in the catalytic Cu surface not being exposed to air. This purportedly avoids oxidation before the electroless Cu deposition is undertaken. After etching of the Al sacrificial seed layer, the catalytic seed layer acts as a catalytic material for electroless Cu deposition. Also, according to he disclosed method, annealing of the seed barrier layer system at 300′C in a vacuum improved adhesion of the seed layer.
Additionally, a small amount of surfactant and stabilizer was added to the copper plating solution in order to control surface tension and to retard hydrogen inclusion in the deposits, as well as to increase solution stability. Examples of surfactants are: RE 610, polyethylenglycol,NCW-601A, Triton X-100. Examples of stabilizers disclosed are: Neocuproine, 2,2′ dipyridyl, CN—, Rhodanine.
Other patents which describe and teach electroless metallization techniques include U.S. Pat. No. 5,500,315; U.S. Pat. No. 5,310,580; U.S. Pat. No. 5,389,496; and U.S. Pat. No. 5,139,818, all of which are hereby incorporated by reference.
Whereas electroless plating of copper on microelectronic workpieces offers advantages, such as good conformality the electroless deposition rate of copper is generally lower than that produced by electroplating. Accordingly, another aspect of the present invention recognizes the desirability of achieving the advantageous conformality of the deposited copper in small and/or high aspect ratio features, such as vias and trenches, while at the same time having an increased overall deposition rate for increased microelectronic production throughput. This aspect of the present invention also recognizes the desirability of providing an electroless plating reactor which can be incorporated into an automated microelectronic processing tool.